1. Field of the Invention
This invention relates to data processing systems employing data buffers, and more particularly to the use of lock bits in data buffers to access logic records.
2. Description of the Prior Art
It is known to use lock bits in the entry of data buffers for controlling access to logic record pieces. The lock bits are presently stored along with the associated logic record pieces in the translation lookaside buffer (TLB) such that the TLB must include space for such lock bits.
A number of prior art patents are known which involve translation lookaside buffers; however, none of the references relate to storing lock bits in a separate array rather than storing the lock bits with each TLB entry.
For example, U.S. Pat. No. 4,096,573 entitled DLAT SYNONYM CONTROL MEANS FOR COMMON PORTIONS OF ALL ADDRESS SPACES, issued June 20, 1978 to Heller et al relates to the use of special controls in a processor to prevent synonym entries in a translation lookaside buffer for a system which has buffer entries that can concurrently translate virtual page addresses in multiple address spaces into real main storage page frame addresses.
U.S. Pat. No. 4,136,385 entitled SYNONYM CONTROL MEANS FOR MULTIPLE VIRTUAL STORAGE SYSTEMS, issued Jan. 23, 1979 to Gannon et al, is similar to the above but describes a different type of controls.
U.S. Pat. No. 4,145,738 entitled PLURAL VIRTUAL ADDRESS SPACE PROCESSING SYSTEM, issued Mar. 20, 1979 to Inoue et al, describes a system having a plurality of virtual address spaces wherein a virtual address is translated into a real address for accessing a main memory and the translation result is stored in a translation lookaside buffer, as in a processing system having a single virtual address space. Thereafter, in the case of the same virtual address as the above, the translation lookaside buffer is retrieved to translate the virtual address into a real address.
In U.S. Pat. No. 4,347,565 entitled ADDRESS CONTROL SYSTEM FOR SOFTWARE SIMULATION, issued Aug. 31, 1982 to Kaneda et al, an address control system is described for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer.
U.S. Pat. No. 4,332,010 entitled CACHE SYNONYM DETECTION AND HANDLING MECHANISM, issued May 25, 1982 to Messina et al describes a fast synonym detection and handling mechanism for a cache directory utilizing virtual addressing in data processing systems. The cache directory is divided into groups of classes as a function of the number of cache address bits derived from a translatable part of a requested logical address. The cache address is derived from a non-translatable part of the logical address which is used to simultaneously select one class in each of the groups. The selected class entries are simultaneously compared with one or more dynamic lookaside address translator translated absolute addresses. Compare signals, one for each class entry per absolute address, are routed to a synonym detection circuit.
Other U.S. patents in this area which describe address translation and register accessing using keys are 4,037,214 and 4,170,039.
In co-pending U.S. patent application filed Mar. 23, 1981 by Chan et al, entitled CACHE LOCKING CONTROLS IN A MULTIPROCESSOR, now U.S. Pat. No. 4,513,367, a lock bit array with four lock bits representing four line entries in a cache processor directory, is shown as being separate from the cache processor directory so that all the lock bits can be reset simultaneously. In this system, the number of lock bits is not reduced.